What it is

The T2 is Apple's custom security and power management coprocessor found on Intel-based Mac logic boards (2016–2019 models). It sits at the intersection of firmware security, power sequencing, thermal control, and SMBus communications. The chip handles early boot authentication, manages the PPBUS_G3H and PP3V3_G3H rails, controls fan speed via pulse-width modulation, and monitors PMIC outputs through INA3221 current sensors.

The T2 communicates with the main CPU via isolated SMBus lines and enforces signed boot requirements. From a board repair perspective, it is a single point of failure for the entire power-on sequence. No startup activity will occur if the T2 cannot initialize its power domains or load firmware from the embedded NAND flash.

Typical failure modes include corrupted firmware, bad decoupling capacitors on its supply rails, open filter inductors in its VRM circuit, and fractured solder joints on the BGA package. The T2 does not tolerate repeated hard power cycles during diagnosis.

In practice

When a Mac board fails to power on, the T2 is the first suspect. If you measure 0V or unstable ripple on PP3V3_G3H at C7139 (typical bulk cap location), the T2's internal regulator or its input rail is dead. Check the PPBUS_G3H input: if present and stable, probe the T2 feedback divider network—usually two 100k resistors to ground near the output pins.

On boot, the T2 asserts a weak pull-down on the CPU reset line. If reset is held low indefinitely after SMC clock pulses appear, the T2 firmware load has stalled. Measure with a DMM on SMC_CLK and SMC_DATA while holding power button for 10 seconds—you should see modulation. No toggling indicates SPI NAND failure or corrupted bootloader.

Use an oscilloscope to verify 1.8V I2C signaling on the SMBus rails. Capacitive loading from a shorted INA3221 address line will prevent the T2 from communicating with power monitors, triggering a shutdown after 2–3 seconds. Disconnect the INA IC and retry: if the board advances further, you've isolated the culprit.

The T2 package is fragile. Never probe directly on BGA pads; use adjacent test points. Thermal cycling stress from repeated reflow attempts can fracture internal solder balls. If a board boots intermittently after rework, perform X-ray inspection of the T2 package before declaring the chip good.

Test Point / Rail Expected Value (Powered Off) Expected Value (Active) Fault Indicator
PPBUS_G3H input to T2 0V 12.6V ± 0.2V Stuck at 0V; SMC not asserting power enable
PP3V3_G3H regulated output 0V 3.30V ± 0.05V Sagging to 2.8V; ESR failure or load short
T2 core supply (PPVCORE_S0 when active) 0V 0.9V ± 0.03V Floating; PMIC gate drive missing
SMC_CLK line (JTAG) 1.8V (idle) 500 kHz clock during boot No toggle; bootloader stuck or missing
INA_SDA / INA_SCL (SMBus) 1.8V (pullup) 0.3–1.8V (I2C toggle) Held low; slave device shorted or unresponsive
T2 reset output (to CPU) 0V (asserted low) 1.0V ± 0.1V (released) Stuck low after 5 seconds; power sequence timeout
⚠ T2 firmware corruption is not user-repairable. If the T2 NAND flash is corrupted and the recovery SPI path is unavailable, the board will require factory DFU (Device Firmware Update) mode or donor IC transplant. Attempting blind EEPROM overwrite will likely brick the chip permanently.

See also

Related terms in this glossary: