820-02521 Voltage Reference — MacBook Air M1 2020
Complete DC voltage map for the 820-02521 logic board under normal operating conditions across all power states (S5 standby, S0 active, and sleep modes). Use this reference to diagnose voltage rail failures, bootloop, and no-power conditions. All measurements taken at test points and via-probe under no-load conditions where noted; adjust for actual load conditions.
Main Voltage Rails
| Rail Name | Power State | Expected Voltage | Measurement Point | Notes |
|---|---|---|---|---|
PP5V0 |
S5 (Standby) | 5.0–5.1 V | USB-C power input TP | Primary 5 V rail from USB-C; supplies most auxiliary circuits |
PP5V0 |
S0 (Active) | 5.0–5.1 V | USB-C power input TP | Should remain stable under load; ripple <100 mV typical |
PP3V3 |
S5 (Standby) | 3.25–3.35 V | U6500 output pin / main 3V3 bus | Generated from PP5V0 via primary buck; critical for all digital logic |
PP3V3 |
S0 (Active) | 3.25–3.35 V | U6500 output pin / main 3V3 bus | Must be stable; 50–75 mA typical current under load |
PP1V8_LOGIC |
S5 (Standby) | 1.75–1.85 V | U6700 output / logic core rail | Generated from PP3V3; supplies SoC I/O, memory controllers |
PP1V8_LOGIC |
S0 (Active) | 1.75–1.85 V | U6700 output / logic core rail | Typical 200–300 mA under full CPU load; tight tolerance required |
PP1V2_CORE |
S5 (Standby) | 0 V | U6100 output (main VDD) | CPU core voltage; off during standby; enable via VDD_ENABLE signal |
PP1V2_CORE |
S0 (Active) | 1.15–1.25 V | U6100 output (main VDD) | Primary M1 SoC core rail; 30–50 A typical under load; very dynamic |
PP0V85_SOC |
S5 (Standby) | 0 V | U6200 output | SoC analog supply; off during standby |
PP0V85_SOC |
S0 (Active) | 0.82–0.88 V | U6200 output | Supplies analog blocks within SoC; tight regulation required |
PP2V5_ANA |
S5 (Standby) | 2.45–2.55 V | U7200 output / analog block | Analog supply for storage subsystem and audio codec |
PP2V5_ANA |
S0 (Active) | 2.45–2.55 V | U7200 output / analog block | Remains on in all states; stable 5–10 mA load |
PP1V0_RAM |
S5 (Standby) | 0 V | U6300 output | LPDDR4X supply; off during standby to save power |
PP1V0_RAM |
S0 (Active) | 0.95–1.05 V | U6300 output | Memory core voltage; 3–8 A typical; tight tolerance |
PP1V2_RAM_TERM |
S5 (Standby) | 0 V | U6350 output | LPDDR4X termination supply; off during standby |
PP1V2_RAM_TERM |
S0 (Active) | 1.15–1.25 V | U6350 output | Termination for memory data lines; 1–2 A typical |
PP3V3_BT |
S5 (Standby) | 3.25–3.35 V | U7500 output / Bluetooth module | Supplies Bluetooth/Wi-Fi combo module; always on for wake |
PP3V3_BT |
S0 (Active) | 3.25–3.35 V | U7500 output / Bluetooth module | Typical 100–150 mA under Wi-Fi activity |
PP5V0_USB |
S5 (Standby) | 5.0–5.1 V | USB-C connector, VBUS test pad | USB port power supply; gated via USB power delivery control |
PP5V0_USB |
S0 (Active) | 5.0–5.1 V | USB-C connector, VBUS test pad | Can supply up to 3 A per port depending on PD contract |
PP3V3_NVME |
S5 (Standby) | 3.25–3.35 V | U8100 output / SSD module | SSD supply; off in deep sleep, on in standby for fast wake |
PP3V3_NVME |
S0 (Active) | 3.25–3.35 V | U8100 output / SSD module | Typical 50–200 mA depending on SSD activity |
PP1V8_NVME |
S5 (Standby) | 0 V | U8150 output / SSD core | SSD core voltage; off in standby |
PP1V8_NVME |
S0 (Active) | 1.75–1.85 V | U8150 output / SSD core | Typical 20–50 mA under I/O activity |
PP5V0_LIGHTING |
S5 (Standby) | 0 V | Keyboard backlight FET gate / controller | Keyboard backlight supply; always off in standby |
PP5V0_LIGHTING |
S0 (Active) | 4.9–5.1 V | Keyboard backlight FET gate / controller | PWM-controlled; 0–500 mA depending on brightness |
PP3V3_DISCRETE |
S5 (Standby) | 3.25–3.35 V | Discrete GPIO power rail / sensor supply | Powers motion sensors, SMC peripherals; always on |
PP3V3_DISCRETE |
S0 (Active) | 3.25–3.35 V | Discrete GPIO power rail / sensor supply | Typical 20–50 mA; used by accelerometer, gyro, ambient light |
PP1V2_CAM |
S5 (Standby) | 0 V | U9100 output / camera sensor | Webcam analog supply; off during standby |
PP1V2_CAM |
S0 (Active) | 1.15–1.25 V | U9100 output / camera sensor | Only on when camera active; typical 50–100 mA during video |
PPVCCIO_CAM |
S5 (Standby) | 0 V | U9110 output / camera I/O | Webcam I/O supply; off during standby |
PPVCCIO_CAM |
S0 (Active) | 1.75–1.85 V | U9110 output / camera I/O | Active when camera enabled; typical 30–60 mA |
Key Enable Signals
| Signal Name | Expected State (S5) | Expected State (S0) | Control Source | Notes |
|---|---|---|---|---|
SMC_ENABLE |
Low (0 V) | High (~3.3 V) | SMC / EC firmware | Master enable from System Management Controller; gates all major rails |
VDD_ENABLE |
Low (0 V) | High (~3.3 V) | SMC via U6100 EN pin | Main SoC core voltage enable; high impedance during standby |
VDD_ANA_ENABLE |
Low (0 V) | High (~3.3 V) | SMC via U6200 EN pin | SoC analog supply enable; gated independently |
VRAM_ENABLE |
Low (0 V) | High (~3.3 V) | SMC via U6300 EN pin | LPDDR4X supply enable; off in deep sleep for power saving |
NVME_ENABLE |
Low (0 V) | High (~3.3 V) | SMC via U8100 EN pin | SSD supply enable; may remain on in standby for quick wake |
BT_ENABLE |
High (~3.3 V) | High (~3.3 V) | SMC via GPIO line | Bluetooth module always powered for wireless wake; controlled by firmware |
CAM_ENABLE |
Low (0 V) | Low / High (~0–3.3 V) | SMC / SoC I2C control | Camera supply and I/O enable; gated only when actively in use |
LIGHTING_EN |
Low (0 V) | PWM (0–3.3 V) | SoC PWM output to FET gate | Keyboard backlight enable; PWM frequency ~1 kHz typical |
Power State Voltage Summary
| Power State | Description | Core Rails On | Peripheral Rails On | Typical Current Draw |
|---|---|---|---|---|
| S5 | Standby (AC connected, battery present) | PP3V3, PP2V5_ANA, PP3V3_BT, PP3V3_DISCRETE | PP5V0, PP5V0_USB, PP3V3_NVME | <100 mA |
| S4 | Hibernation / Memory Sleep (rare on M1) | PP3V3, PP2V5_ANA, VRAM (minimal) | PP3V3_DISCRETE, PP3V3_BT | 50–80 mA |
| S3 | Sleep (SoC/RAM clocks gated, displays off) | PP3V3, PP2V5_ANA, PP1V0_RAM (minimal) | PP3V3_BT, PP3V3_DISCRETE, PP3V3_NVME | 80–120 mA |
| S0 | Active / Full power | All rails | All rails | 5–15 A (depends on CPU/GPU load) |
| G3 | Mechanical off / Battery removed | None | None | 0 mA (ideal); <5 µA leakage |
Common Fault Voltages
| Symptom | Rail(s) to Check | Expected Voltage | Fault Indication | Possible Cause |
|---|---|---|---|---|
| No power / board dead | PP5V0, PP3V3 | 5.0–5.1 V, 3.25–3.35 V | 0 V on both rails | Dead main buck U6500, PMIC damaged, or USB-C connector fault |
| No USB power delivery / won't charge | PP5V0_USB, USB data lines D+/D− | 5.0–5.1 V (negotiated) | 0 V or floating | PD controller U7000 failure, USB-C port damage, or firmware issue |
| Won't boot / bootloop | PP1V2_CORE, PP0V85_SOC, PP1V8_LOGIC | 1.15–1.25 V, 0.82–0.88 V, 1.75–1.85 V | 0 V (never enabled) or oscillating (unstable) | SoC core buck U6100 dead, enable signal stuck low, or SoC damaged |
| Instant shutdown / kernel panic on load | PP1V2_CORE, VRAM (PP1V0_RAM) | 1.15–1.25 V, 0.95–1.05 V | Voltage sags >150 mV under load or ripple >200 mV | Weak buck inductor, shorted capacitor, or excessive load (SoC short) |
| SSD not detected / NVME error | PP3V3_NVME, PP1V8_NVME, SSD_EN signal | 3.25–3.35 V, 1.75–1.85 V, 3.3 V | 0 V on either NVME rail or enable stuck low | SSD buck U8100/U8150 failure, enable signal not driven, or SSD module short |
| Wi-Fi / Bluetooth dead | PP3V3_BT, BT_EN signal | 3.25–3.35 V, 3.3 V | 0 V on PP3V3_BT or signal stuck low | Bluetooth module buck U7500 failure, enable signal not driven, or module damaged |
| Keyboard backlight won't turn on | PP5V0_LIGHTING, LIGHTING_EN PWM | 4.9–5.1 V, 0–3.3 V PWM | 0 V on rail or PWM always low | Lighting buck dead, FET gate driver U9200 shorted, or SoC PWM output dead |
| Camera won't enumerate / black video | PP1V2_CAM, PPVCCIO_CAM, CAM_EN | 1.15–1.25 V, 1.75–1.85 V, 3.3 V | 0 V on either supply or enable stuck low | Camera buck U9100/U9110 failure, I2C enable line stuck, or sensor damaged |
| RAM not detected / memory error on boot | PP1V0_RAM, PP1V2_RAM_TERM, VRAM_EN | 0.95–1.05 V, 1.15–1.25 V, 3.3 V | 0 V on either rail or enable stuck low | RAM buck U6300/U6350 failure, enable line stuck, or LPDDR4X module short |
| Random resets / watchdog timeout | PP1V8_LOGIC, PP3V3, SMC reset line | 1.75–1.85 V, 3.25–3.35 V, 3.3 V | Sagging or oscillating voltage under load; reset line chattering | Weak logic buck U6700, shorted bulk capacitor, or SMC watchdog firmware issue |
| No USB ports work | PP3V3, USB controller supply (via U8000) | 3.25–3.35 V | 0 V or sagging to <3.0 V | USB controller buck failure or main 3V3 rail short |
| Audio codec no sound / no mic | PP2V5_ANA, PP1V8_LOGIC (codec I/O) | 2.45–2.55 V, 1.75–1.85 V | 0 V on either rail | Analog buck U7200 dead or codec power delivery issue |
| Display won't light / backlight dark | PP5V0, PP3V3 (display power) | 5.0–5.1 V, 3.25–3.35 V | 0 V on either rail or sagging under display load | Display power FET shorted, LVDS buck dead, or main 5V0/3V3 undersupplied |
Notes & Caveats
- Measurement technique: Use a high-impedance multimeter (10 MΩ+) on DC voltage mode. Probe power rails via test points or directly on buck output pins; avoid the SoC balls themselves (risk of micro-junction damage). For low-voltage rails (<1 V), use an oscilloscope to catch transients missed by slower multimeters.
- Load state dependency: Most core rails (VDD, VRAM, SoC analog) exhibit significant voltage sag under full CPU/GPU load (±100–150 mV typical). A static measurement under no-load is not sufficient for diagnosing a loaded system; always measure during the specific failure condition (e.g., during boot, during a 3D benchmark).
- Probe tip cleanliness: 820-02521 uses 0.4 mm pitch fine-pitch BGA and micro-vias. A dirty or oxidized probe tip will create false readings (typically 0.1–0.3 V lower than actual). Clean probe tips with isopropyl alcohol and inspect under magnification before critical measurements.
- Temperature compensation: Voltage regulators on this board are calibrated for 25 °C. Thermal variations (especially around the SoC during heavy load) can shift output by ±50 mV. Avoid measuring immediately after thermal stress testing.
- SMC sequencing: The SMC firmware enforces strict sequencing of rail enables. A rail showing 0 V when it should be on typically means the enable line from the SMC is stuck low or the SMC itself is not responding to power-on signals. Check
SMC_ENABLE,VDD_ENABLE, and other gate signals before replacing bucks.
See Also
- 820-02521 Diode Mode Reference — component-level resistance and diode mode testing for fault isolation
- 820-02521 Power-On Sequencing — timing, order, and SMC signal dependencies for boot
- SMC Enable Signals (M1 Common) — cross-board reference for SMC-controlled enables
- U6100 Main VDD Buck Controller — datasheet pinout and tuning tips
- U6500 Primary 5V to 3V3 Converter — schematic and typical failure modes
- Voltage Rail Naming Convention — how to decode PP* prefix and subscripts
- M1 SoC Power Domains Overview — which rails are critical for each subsystem
- USB-C Power Delivery Control (820-02521) — how to diagnose failed charging
820-02521 voltages m1 macbook-air-2020